For many applications, such as system-on-chip, it is desirable to integrate logic devices and interface circuits based upon metal-oxide-semiconductor field-effect transistors (MOSFET) and non-volatile memory (NVM) transistors on a single chip or wafer. This integration can seriously impact both the MOS transistor and NVM transistor fabrication processes. MOS transistors are typically fabricated using a standard or baseline complementary-metal-oxide-semiconductor (CMOS) process flows, involving the formation and patterning of conducting, semiconducting and dielectric materials. The composition of these materials, as well as the composition and concentration of processing reagents, and temperature used in such a CMOS process flow are stringently controlled for each operation to ensure the resultant MOS transistors will function properly.
Non-volatile memory devices include non-volatile memory transistors, such as silicon-oxide-nitride-oxide-silicon (SONOS) based transistors, including charge-trapping gate stacks in which a stored or trapped charge changes a threshold voltage of the NVM transistor to store information as a logic 1 or 0. Charge-trapping gate stack formation involves the formation of a nitride or oxynitride charge-trapping layer(s) sandwiched between two dielectric or oxide layers typically fabricated using materials and processes that differ significantly from those of the baseline CMOS process flow, and which can detrimentally impact or be impacted by the fabrication of the MOS transistors. In particular, forming a gate oxide or dielectric of a MOS transistor may significantly degrade performance of a previously formed charge-trapping gate stack by altering a thickness or composition of the charge-trapping layer(s). In addition, this integration can seriously impact the baseline CMOS process flow, and generally requires a substantial number of mask sets and process steps, which add to the expense of fabricating the devices and can reduce yield of working devices.
Besides, it is imperative for the integrated fabrication process to be able to control the thickness of top oxide of NVM transistors in order to meet requirements such as threshold voltages Vts and/or equivalent oxide thickness (EOT) requirements while satisfying gate oxide thickness requirements of MOS transistors, especially if those MOS transistors are high voltage input/output (HV I/O) transistors.